High power efficiency is required in power amplifier apparatuses for wireless communication. It is necessary to make the power amplifier work at a nonlinear region to increase the power efficiency of the power amplifier. On the other hand, when a power amplifier is used in a linear region, the power efficiency decreases. Thus, linearity and power efficiency are considered as conflicting characteristics. Hence, various distortion compensation methods have been proposed for a power amplifier apparatus to realize both linearity and power efficiency in a power amplifier.
A predistorter is known as one of the distortion compensation methods. This method is adding the inverse characteristic of the distortion of the power amplifier to the amplifier input signal, and canceling the distortion at the power amplifier output.
FIG. 1 is an exemplary configuration diagram of an existing power amplifier apparatus.
A complex-data transmission signal Tx(t) is supplied to a terminal 1. This transmission signal is supplied to a predistortion signal generator 3 and an address generator 4 within a look up table (LUT) distortion compensation unit 2. The address generator 4 generates the address of an LUT 5 from, for example, the amplitude of the transmission signal Tx(t). The address generator 4 supplies the generated address to the LUT 5. Thereby, the LUT 5 reads distortion compensation coefficients for a series distortion compensation method in accordance with the address. The LUT 5 supplies the distortion compensation coefficients to the predistortion signal generator 3.
The predistortion signal generator 3 multiplies an input signal by the distortion compensation coefficients to generate a predistortion signal. Note that complex multiplication is performed for complex data. The predistortion signal generator 3 supplies the predistortion signal to a DAC 6 and writes the predistortion signal into a memory 7. The DAC 6 supplies the predistortion signal having been converted into an analog signal to a power amplifier 8. The power amplifier 8 amplifies the power of the supplied signal. The amplified signal is transmitted through a directional coupler 9 and an antenna 10.
Part of the output signal of the power amplifier 8 is extracted from the directional coupler 9 and digitized by an ADC 11. The digitized signal is written into a memory 12 as a feedback signal. The feedback signal read from the memory 12 is supplied to a series distortion compensator 14 within a coefficient updating unit 13. The series distortion compensator 14 performs series operations on the feedback signal and generates a predistortion signal. The series distortion compensator 14 supplies the generated predistortion signal to a subtracter 15.
The memory 7 supplies the subtracter 15 with the predistortion signal read in synchronization with the above-described feedback signal. The subtracter 15 subtracts the predistortion signal of the feedback signal from the predistortion signal supplied from the memory 7 to obtain an error. The subtracter 15 supplies the obtained error to the series distortion compensator 14. The series distortion compensator 14 performs adaptive control so as to reduce and/or minimize the error. For example, the series distortion compensator 14 computes the coefficients of a Volterra series. An LUT coefficient generator 16 generates LUT distortion compensation coefficients from the coefficients of the Volterra series output from the series distortion compensator 14. The LUT coefficient generator 16 supplies the LUT 5 with the address of the LUT 5 and the LUT distortion compensation coefficients. Thereby, the LUT distortion compensation coefficients of the LUT 5 are updated.
U.S. Pat. No. 6,903,604, U.S. Pat. No. 6,504,425, U.S. Pat. No. 6,141,390, and U.S. Pat. No. 7,627,293 propose techniques to collect and analyze a predistortion signal and a feedback signal, thereby controlling the parameters of a predistortion signal generation polynomial.